IP Law Daily Claims for method of designing integrated circuits not invalidated by prior art
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Monday, April 24, 2017

Claims for method of designing integrated circuits not invalidated by prior art

A Patent Trial and Appeal Board decision finding invalid two independent claims of a patent for a method of designing the layout of an integrated circuit was not supported by substantial evidence, the U.S. Court of Appeals for the Federal Circuit has held. Prior art references cited by the Board did not teach or suggest the patented methods for "flattening" the layout by removing levels of hierarchy in a logic tree. The court reversed the Board’s invalidity determination with respect to both of the independent claims and nine dependent claims (Synopsys, Inc. v. ATopTech, Inc., April 24, 2017, Moore, K.).

Patent-in-suit. Synopsys, Inc., owned U.S. Patent No. 6,567,967 ("the ’967 patent"), which disclosed a method for designing the layout of a large integrated circuit. Two types of components were at issue: hard blocks and soft blocks (sometimes referred to as hard or soft "macros"). A hard block had predefined physical characteristics such as shape, size, layout, and timing. A soft block had an arbitrary shape, and its size was determined by the number and size of smaller cells within it. The claimed method was intended to improve circuit performance by splitting large components into smaller sub-components that could be designed individually, then optimizing the connections between sub-components.

One method disclosed by the ’967 patent was to remove levels of hierarchy in a logic tree. The bottom level of a tree was the "leaf level," and "atomic blocks" sat above the leaf level. Claim 1 required "flattening each of said plurality of hierarchically arranged branches by eliminating superfluous levels of hierarchy above said atomic blocks." Claim 32 required "determining optimal placement of each of the hard blocks, if any, within the predefined area".

ATopTech, Inc., petitioned the Board for inter partes review (IPR) of independent claims 1 and 32 of the ’967 patent. The Board instituted IPR and found that claim 1 was obvious in light of a combination of two prior art references, and claim 32 was anticipated by one of the references. Synopsys appealed.

Claim 1—obviousness. The prior art references at issue were two publications: Carol A. Fields, Creating Hierarchy in HDL-Based High Density FGPA [sic] Design, Euro-DAC ’95, 594–99 (Sep. 18–22, 1995) ("Fields") and Hsiao-Pin Su, et al., Performance-Driven Soft-Macro Clustering and Placement by Preserving HDL Design Hierarchy, Proceedings, 1998 International Symposium on Physical Design: ISPD-98, 12–17 (April 8, 1998) ("Su"). In the Board’s view, a person of ordinary skill in the art would have understood a combination of Fields and Su to teach or suggest the elimination of a level of hierarchy above the atomic blocks. According to the Federal Circuit, this determination was not supported by substantial evidence.

First, Fields did not teach or suggest eliminating a superfluous level of hierarchy, the court said. Not only did Fields fail to teach "flattening" and "eliminating superfluous levels of hierarchy," it taught expanding the level that ATopTech contended was removed. No levels were eliminated, and Fields taught that a flatter design would be "difficult or impossible to route".

Second, the court said, the figures in Su that the Board cited did not support the Board’s conclusion that Su taught or suggested or suggests elimination of a level of hierarchy above the atomic blocks. There was no indication that the cited figures referred to or illustrated one another, and the figures appeared to be unrelated. The text did not support the interpretation that the second figure depicted the layout of the first figure with a flattened structure. Accordingly, the court reversed the obviousness determination regarding claim 1.

Claim 32—anticipation. The Board found that Su expressly disclosed claim 32’s requirement of "determining optimal placement of each of the hard blocks." The Board reasoned that Su taught using a commercial floorplanner to place hard blocks, and Su taught that its overall layout determination method was "performance-driven," so Su taught optimal placement of hard blocks. The court disagreed. Su was focused on the placement of soft blocks and disclosed very little about the placement of hard blocks. It only referred to hard blocks in teaching that "we use a commercial floorplanner to perform macro floorplanning to determine the locations of hard macros …." and that "each hard-macro is assigned into its corresponding region according to the floorplanning result." Su never disclosed determining the optimal placement of hard blocks. Therefore, the Board’s finding of anticipation was reversed.

The case is Nos. 2016-1956 and 2016-1957.

Attorneys: Matthew J. Silveira (Jones Day) for Synopsys, Inc. Philip William Marsh (Arnold & Porter, LLP) for ATopTech, Inc.

Companies: Synopsys, Inc.; ATopTech, Inc.

MainStory: TopStory Patent FedCirNews

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